1. Field of the Invention
The present invention relates generally to electronic amplifier circuits implemented using complementary metal oxide semiconductor (CMOS) technology. More specifically, the present invention relates to a CMOS amplifier circuit providing improved performance characteristics including automatic cancellation of offset voltage.
2. Description of the Prior Art
In ideal linear amplifier circuits, each differential pair of transistors in each amplifying stage of a chain is perfectly balanced so that there is no offset voltage which can lead to errors in the linear relationship between the input signal level and output signal level of the amplifier circuit. However, due to imperfect processing characteristics combined with the effects of temperature variations, an offset voltage, V.sub.OS, typically arises between each differential pair of transistors.
It is particularly difficult to achieve balanced characteristics between differential pairs of transistors in amplifier circuits implemented using complementary metal oxide semiconductor (CMOS) technology. While bipolar junction transistor (BJT) technology, which allows for better processing control, may be used to implement amplifier circuits for many types of applications, CMOS technology is commonly preferred because of lower cost.
The linearity of an amplifier circuit is particularly important in data processing applications wherein the signal received at the input of the amplifier circuit is very small. Therefore, in such applications, it is very desirable that each differential pair of transistors be very well balanced, having minimal offset voltage. It is also particularly important in such applications that there be minimal DC wandering.
A fiber optic receiver is one example of an electronic system requiring a linear amplifier circuit for amplifying an input signal which is very small. A fiber-optic receiver typically includes: a photodiode for receiving the fiber-optic signal, and for generating an electrical analog signal; a pre-amplifier responsive to the analog signal, and operative to generate a pre-amplified analog signal; a post-amplifier responsive to the pre-amplified analog signal, and operative to generate a post-amplified analog signal; and a data slicer for converting the post-amplified analog signal to a digital data signal.
The signal level of the pre-amplified analog signal received by the post-amplifier is typically only a few millivolts (mV). Typically, the post-amplifier includes a CMOS input stage having a differential pair which is subject to create an offset voltage in the range of tens of millivolts. This problem causes errors in the linearity of the post-amplifier circuit which lead to data errors as the post-amplified analog signal is processed by the data slicer. The data slicer cannot provide an accurate digital data signal unless the offset voltage of the post-amplifier circuit is properly canceled. Additionally, an input port of the post amplifier may be coupled with an AC coupling capacitor which may also have a DC wandering effect which needs to be compensated in order to generate digital signal levels required for data processing including clock/data recovering.
Typical prior art post-amplifiers include: an automatic gain control amplifier (AGC amplifier) having an input port for receiving an input data signal, and an output port for providing an amplified data signal; and a feedback circuit coupled between the output port and the input port of the AGC amplifier. To reduce the undesirable effects of offset voltage, the feedback circuit in prior art post-amplifiers typically includes: a peak detection circuit connected to receive the amplified data signal from the output port of the AGC amplifier, and being operative to sense peak levels of the differential pair of amplified data signal levels, and being further operative to provide an offset correction signal which is proportional to the voltage offset between the differential pair of amplified data signal levels; and an error amplifier for amplifying the offset signal, and providing an amplified offset signal back to the input port of the AGC amplifier in a negative feedback manner in order to cancel the voltage offset arising in the AGC amplifier.
One problem associated with the use of a peak detection circuit in a negative feedback path for canceling offset voltage arising in a post-amplifier is that peak detection circuits can provide an inaccurate indication of the actual offset voltage in the AGC amplifier due to a variety of problems including the inherent voltage offset of the peak detection circuitry itself. Another problem associated with the use of a peak detection circuits for canceling voltage offset in a post-amplifier is that peak detection circuits are complex and expensive.
What is needed is an accurate and cost effective method and apparatus for canceling voltage offset arising in an amplifier circuit.